电压检测MAX110ACPE[1](9)

Low-Cost, 2-Channel, ±14-Bit Serial ADCs

_______________Detailed Description

to theADC. The up/down counter clocks data in fromThe MAX110/MAX111 ADC converts low-frequencythe comparator at the oversampling clock rate andanalog signals to a 16-bit serial digital output (14 dataaverages the pulse-width-modulated (PWM) squarebits, a sign bit, and an overrange bit) using a first-orderwave to produce the conversion result. A 16-bit staticsigma-delta loop (Figure 1). The differential input volt-shift register stores the result at the end of the conver-age is internally connected to a precision voltage-to-sion. Figure 2 shows the ADC waveforms for a differen-current converter. The resulting current is integratedtial analog input equal to 1/2 (VREF+- VREF-). Theand applied to a comparator. The comparator outputresulting comparator and 1-bit DAC outputs are highthen drives an up/down counter and a 1-bit DAC. Whenfor seven cycles and low for three cycles of the over-the DAC output is fed back to the integrator input, thesampling clock.

sigma-delta loop is completed.

Since the analog input signal is integrated over manyDuring a conversion, the comparator output is a Vclock cycles, much of the signal and quantization noiseto VREF-is attenuated. The more clock cycles allowed duringthe magnitude of the differential input voltage applied

REF+square wave; its duty cycle is proportional toeach conversion, the greater the noise attenuation (seeProgramming Conversion Time).

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MAX110/MAX111