电压检测MAX110ACPE[1](6)

Low-Cost, 2-Channel, ±14-Bit Serial ADCsMAX110/MAX111

Note 1:These specifications apply after auto-null and gain calibration. Performance at power-supply tolerance limits is guaranteed

by power-supply rejection tests. Tests are performed at VDD= 5V and VSS= -5V (MAX110).

Note 2:32,768 LSBs cover an input voltage range of ±VREF(15 bits). An additional bit (OFL) is set for VIN> VREF.Note 3:Guaranteed by design. Not subject to production testing.

Note 4:DNL is less than ±2 counts (LSBs) out of 215counts (±14 bits). The major source of DNL is noise, and this can be further

improved by averaging.

Note 5:See 3-Step Calibrationsection in text.

Note 6:VREF= (VREF+- VREF-), VIN= (VIN1+- VIN1-) or (VIN2+- VIN2-). The voltage is interpreted as negative when the voltage at

the negative input terminal exceeds the voltage at the positive input terminal.

Note 7:Conversion time is set by control bits CONV1–CONV4.

Note 8:Tested at clock frequency of 1MHz with the divide-by-2 mode (i.e. oversampling clock of 500kHz). See Typical Operating

Characteristicssection for the effect of other clock frequencies. Also read the Clock Frequencysection.

Note 9:This current depends strongly on CXCLK(see Applications Informationsection).

TIMING CHARACTERISTICS(see Figure 6)

(VDD= 5V, VSS= -5V (MAX110), TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

Note 10:Timing specifications are guaranteed by design. All input control signals are specified with tr= tf= 5ns

(10% to 90% of +5V) and timed from a +1.6V voltage level.

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