电压检测MAX110ACPE[1](13)

Low-Cost, 2-Channel, ±14-Bit Serial ADCsMAX110/MAX111

Figure 8a. SPI/MICROWIRE-Interface Timing

Figure 8b. QSPI Serial-Interface Timing

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Low-Cost, 2-Channel, ±14-Bit Serial ADCs

Table 1. Input Control-Word Bit Map

NO-OPis a zero, the control word is not transferred toWhen PDX is set high, the internal RC oscillator stopsthe control register, the ADC’s configuration remainsshortly after CSreturns high. If the next control wordunchanged, and no new conversion is initiated. Thiswritten to the device has NO-OP= 1 instructing theallows specific ADCs in a “daisy chain” arrangement toADC to convert, BUSY will go low, but because the RCbe reconfigured while leaving the remaining ADCsoscillator is stopped, BUSY will remain low and will notunchanged. Table 1 lists the various ADC control wordallow a new conversion to begin. To avoid this situation,functions.

write a “dummy” control word with NO-OP= 0 and anyOutput data is shifted out of DOUT at the same time thecombination of bits 14-0 in the control word followinginput control word for the next conversion is shifted inthe control word with PDX = 0. With NO-OP= 0, bits 14-(Figure 8).

0 are ignored and the internal state machine resets.On power-up, all internal registers reset to zero.Next, perform a normal 3-step calibration (see Table 3).Therefore, when writing the first control word to theNote that XCLK must be connected to VADC, the data simultaneously shifted out will be zeros.through a resistor (suggested value is 1M DDor GND) when theThe first conversion begins when CSgoes high (NO-OPRC oscillator mode is selected (RCSEL = V= 1). The results are placed in the 16-bit I/O register forresistor is not necessary if the external oscillator modeDD). Thisaccess on the next data-transfer operation.

is used, or if the internal oscillator is not shut down.

Power-Down Mode

Selecting the Analog Inputs

Bits 0 and 1 control the ADC’s power-down mode. If bitBit 4 (CHS) controls which of the two differential inputs0 (PD) is a logic high, power is removed from all analogconnect to the internal ADC inputs (see the Functionalcircuitry except the RC oscillator. A logic high at bit 1Diagram). A logic high selects IN2+ and IN2- while a(PDX) removes power from the RC oscillator. If both bitslogic low selects IN1+ and IN1-. Table 2 shows thePD and PDX are a logic high, or if PD is high andallowable input multiplexer configurations.

RCSEL is low, the supply currents reduce to 4µA. If anexternal XCLK clock continues to run in power-downmode, the supply current will depend on the clock rate.

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MAX110/MAX111