电压检测MAX110ACPE[1](17)

时间：2026-01-22

Low-Cost, 2-Channel, ±14-Bit Serial ADCs

Figure 10a. MAX110 Power-Supply Grounding ConnectionsFigure 10b. MAX111 Power-Supply Grounding Connections

A 100ms conversion time cannot be achieved with eitherIf you wish to use a configuration other than those sug-10,240 CCPC or 20,480 CCPC modes because fOSCgested in Table 6, you can accomplish similar 50Hzwould be below the minimum 250kHz requirement.

and 60Hz line-frequency rejection off-chip by averag-When the gain calibration is performed, the conversioning several conversions.

times change approximately 1% to compensate for themodulator’s gain error. This slightly degrades the line-__________Applications Information

frequency rejection, because the corrected conversionLayout, Grounding, Bypassing

time is no longer an exact multiple of the line frequency.For minimal noise, bypass each supply to GND with aTypically, the rejection of 50Hz/60Hz from the converter0.1µF capacitor. A ground plane should also be placedis 55dB; i.e., if there is 100mV injection at the referenceunder the analog circuitry. To minimize the couplingor the analog input pin, it will cause an uncertainty ofeffects of stray capacitance, keep digital lines as far±0.006%. If the system has large 50Hz/60Hz noise, thefrom analog components and lines as possible. Figureuse of internal auto gain calibration is not recommend-10 shows the suggested power-supply and ground-ed. Instead, gain calibration should be done off-chip,plane connections.

using numerical computation methods.

Table 6. Suggested XCLK Frequencies to Achieve Maximum Rejection of Both 50Hz/60Hz LineFrequencies

MAX110 (tCONVERT= 100ms)MAX111 (tCONVERT= 200ms)81,240 CCPC

102,400 CCPC81,240 CCPC102,400 CCPCDIVIDERDIVIDERRATIO

fXCLKRELATIVERELATIVERATIO

fXCLKRELATIVEXCLKRELATIVE(MHz)ACCURACY

fXCLK(%)

(MHz)ACCURACY

(%)

(MHz)ACCURACY

f(%)

(MHz)ACCURACY