电压检测MAX110ACPE[1](11)

Low-Cost, 2-Channel, ±14-Bit Serial ADCs

MAX110/MAX111

Figure 3a. Connection for External-Clock Mode

Figure 3b. Connection for Internal RC-Oscillator Mode—XCLKconnects to the internal RC oscillator. Note, the pull-up resistoris not necessary if the internal oscillator is never shut down.

ADC Operation

properly if the reference voltage remains within the rec-The output data from the MAX110/MAX111 is arrangedommended voltage range (see Reference Inputs). If thein twos-complement format (Figures 4, 5). The sign bitreference voltage exceeds the recommended input(POL) is shifted out first, followed by the overrange bitrange, the overrange bit may not operate properly.

(OR), and the 14 data bits (MSB first) (see Figure 6).The MAX110 operates from ±5V power supplies andDigital Interface—Starting a Conversion

converts low-frequency analog signals in the ±3VData is transferred into and out of the serial I/O shiftrange when using the maximum reference voltage ofregister by pulling CSlow and applying a serial clockVREF= 3V (VREF= VREF+- VREF-). Within the ±3V inputat SCLK. This fully static shift register allows SCLK torange, greater accuracy is obtained within ±2.5V (seerange from DC to 2MHz. Output data from the ADC isElectrical Characteristicsfor details). Note that a nega-clocked out on SCLK’s falling edge and should be readtive input voltage is defined as VIN-> VIN+. For theon SCLK’s rising edge. Input data to the ADC at DIN isMAX110, the absolute voltage at any analog input pinclocked in on SCLK’s rising edge. A new conversionmust remain within the (Vbegins when CSreturns high, provided the MSB in therange.

SS+ 2.25V) to (VDD- 2.25V)input control word (NO-OP) is a 1 (see Using theThe MAX111 operates from a single +5V supply andMAX110/MAX111 with MICROWIRE, SPI, and QSPIconverts low-frequency differential analog signals in theSerial Interfaces). Figure 6 shows the detailed serial-±1.5V range when using the maximum reference volt-interface timing diagram.

age of VREF= 1.5V. As indicated in the ElectricalCSmust remain high during the conversion(whileCharacteristics, greater accuracy is achieved within theBUSYremains low). Bringing CSlow during the conver-±1.2V range. The absolute voltage at any analog inputsion causes the ADC to stop converting, and maypin for the MAX111 must remain within 0V to Vresult in erroneous output data.

When V> VDD- 3.2V.IN-IN+the input is interpreted as ing the MAX110/MAX111 with SPI, QSPI, and

The overrange bit (OFL) is provided to sense when theinput voltage level has exceeded the reference voltageMICROWIRE Serial Interfaces

level. The converter does not “saturate” until the inputFigure 7 shows the most common serial-interface con-voltage is typically 20% larger. The linearity is not guar-nections. The MAX110/MAX111 are compatible withanteed in this range. Note that the overrange bit works

SPI, QSPI (CPHA = 0, CPOL = 0), and MICROWIREserial-interface standards.

______________________________________________________________________________________

11