电压检测MAX110ACPE[1](16)

Low-Cost, 2-Channel, ±14-Bit Serial ADCsMAX110/MAX111

Figure 9. MAX110/MAX111 Noise Rejection Follows SIN(X) / X Function

Selecting the Oversampling

Clock Frequency

Choose the oversampling frequency, fOSC, carefully toachieve the best relative-accuracy performance from theMAX110/MAX111 (see Typical Operating Characteristics).

clock frequency can be used for best performance.Over the extended and military temperature ranges, theratio of 2 or 4 gives the best performance. See theTypical Operating Characteristicsto observe the effectof the clock divider on the converter’s linearity.

Clock Divider-Ratio Control Bits

Bits 7 and 8 (DV2 and DV4) program the clock-frequency divider network. The divider network sets thefrequency ratio between fXCLK(the frequency of theexternal TTL/CMOS clock or internal RC oscillator) andfOSC(the oversampling frequency used by the ADC).An oversampling clock frequency between 450kHz and700kHz is optimum for the converter. Best perfor-mance over the extended temperature range isobtained by choosing 1MHz or 1.024MHz with thedivide-by-2 option (DV2 = 1) (see the sectionEffectof Dither on INL). To determine the converter’s accura-cy at other clock frequencies, see the TypicalOperating Characteristicsand Table 5.

Effect of Dither on Relative Accuracy

First-order sigma-delta converters require dither forrandomizing any systematic tone being generated inthe modulator. The frequency of the dither source playsan important role in linearizing the modulator. The ratioof the dither generator’s frequency to that of the modu-lator’s oversampling clock can be changed by settingthe DV2/DV4 bits. The XCLK clock is directly used bythe dither generator while the DV2/DV4 bits reduce theoversampling clock by a ratio of 2 or 4. Over the com-mercial temperature range, any ratio (i.e., 1, 2, or 4)between the dither frequency and the oversampling

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50Hz/60Hz Line Frequency Rejection

High rejection of 50Hz or 60Hz is obtained by using anoversampling clock frequency and a clock-cycles/con-version setting so the conversion time equals an inte-gral number of line cycles, as in the following equation:fOSC= fLINEx m / n

where fOSCis the oversampling clock frequency, fLINE= 50Hz or 60Hz, m is the number of clock cycles perconversion (see Table 4), and n is the number of linecycles averaged every conversion.

This noise rejection is inherent in integrating andsigma-delta ADCs, and follows a SIN(X) / X function(Figure 9). Notches in this function represent extremelyhigh rejection, and correspond to frequencies with anintegral number of cycles in the MAX110/MAX111’sselected conversion time.

The shortest conversion time resulting in maximumsimultaneous rejection of both 60Hz and 50Hz line fre-quencies is 100ms. When using the MAX111, use a200ms conversion time for maximum 60Hz and 50Hzrejection andoptimum performance. For either device,select the appropriate oversampling clock frequencyand either an 81,240 or 102,400 clock cycles per con-version (CCPC) ratio. Table 6 suggests the possibleconfigurations.

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