电压检测MAX110ACPE[1](10)

Low-Cost, 2-Channel, ±14-Bit Serial ADCsMAX110/MAX111

Figure 1. Functional Diagram

Oversampling Clock

XCLK internally connects to a clock-frequency dividernetwork, whose output is the ADC oversampling clock,fOSC. This allows the selected clock source (internal RCoscillator or external clock applied to XCLK) to bedivided by one, two, or four (see Clock Divider-RatioControl Bits).

Figure 3 shows the two methods for providing the over-sampling clock to the MAX110/MAX111. In external-clock mode (Figure 3a), the internal RC oscillator isdisabled and XCLK accepts a TTL/CMOS-level clock toprovide the oversampling clock to the ADC.

Select external-clock mode (Figure 3a) by connectingRCSEL to GND and a TTL/CMOS-compatible clock toXCLK (see Selecting the Oversampling ClockFrequency).

In RC-oscillator mode (Figure 3b), the internal RC oscil-lator is active and its output is connected to XCLK(Figure 1). Select RC-oscillator mode by connectingRCSEL to VDD. This enables the internal oscillator andconnects it to XCLK for use by the ADC and externalsystem components. Minimize the capacitive loading onXCLK when using the internal RC oscillator.

Figure 2. ADC Waveforms During a Conversion

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