电压检测MAX110ACPE[1](15)

Low-Cost, 2-Channel, ±14-Bit Serial ADCs

3-Step Calibration

Automatic gain calibration is not allowed in theThe data sheet electrical specifications apply to the102,400 cycles per conversion mode(seedevice after optional calibration of gain error and offset.Programming Conversion Time). In this mode, calibra-Uncalibrated, the gain error is typically 2%.

tion can be achieved by connecting the reference volt-Table 3 describes the three steps required to calibrateage to one input channel and performing a normalthe ADC completely.

conversion. Subsequent conversion results can be cor-Once the ADC is calibrated to the selected channel, setrected by software.Do not issue a NO-OPcommandCAL = 0 and NUL = 0 and leave CHS unchanged in thedirectly following the gain calibration, as the cali-next control word to perform a signal conversion on thebration data will be lost.

selected analog input channel.

Programming Conversion Time

Calibrate the ADC after the following operations:The MAX110/MAX111 are specified for 12 bits of accu-—when power is first applied

racy and up to ±14 bits of resolution. The ADC’s resolu-tion depends on the number of clock cycles allowed—if the reference common-mode voltage changes

during each conversion. Control-register bits 9–12—

if the common-mode voltage of the selected input(CONV1–CONV4) determine the conversion time bychannel varies significantly. The CMRR of the analogcontrolling the nominal number of oversampling clockinputs is 0.25LSB/V.

cycles required for each conversion (OSCC/CONV).—after changing channels (if the common-mode volt-Table 4 lists the available conversion times and result-ages of the two channels are different)

ing resolutions.

—

after changing conversion speed/resolution.

To program a new conversion time, perform a 3-stepcalibration with the appropriate CONV1–CONV4 data—after significant changes in temperature. The offsetused in Table 3. The ADC is now calibrated at the newdrift with temperature is typically 0.003µV/°C.

conversion speed/resolution.

Table 4. Available Conversion Times

CLOCK CYCLES

NOMINAL CONVERSION TIME

CONVERSIONCONV4CONV3CONV2CONV1PER

RCSEL = GND, DV2 = DV4 = 0, XCLK = 500kHz

RESOLUTION

CONVERSION(ms)

(Bits)100110,24020.4812 + POL001120,48040.9613 + POL011081,920163.8414 + POL0

102,400*

204.80

14 + POL

* Gain-calibration mode is not available with 102,400 clock cycles/conversion selected.

Table 5. Clock Divider-Ratio Control

DV2DV4DESCRIPTION

00XCLK or internal RC oscillator connects directly to the ADC; fOSC= fXCLK.

01XCLK or internal RC oscillator is divided by 4 and connects to the ADC; fOSC= fXCLK ÷4.10XCLK or internal RC oscillator is divided by 2 and connects to the ADC; fOSC= fXCLK ÷2.1

1

Not allowed

Clock duty cycles of 50% ±10% are recommended.

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MAX110/MAX111