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256MB, 512MB Registered DIMMs DDR2 SDRAM

Functional Block Diagram: 512MB, 64Mx72 Module(populated as 1 rank of x4 DDR2 SDRAMs) M393T6450FG(Z)0 / M393T6450FG(Z)3 / M393T6450FZA

VSSDQS0DQS0

DM

DQSDM0/DQS9NC/DQS9

DM

CS

DQSDQS

DQ0DQ1DQ2DQ3DQS1DQS1

DQ8DQ9DQ10DQ11DQS2I/O 0I/O 1I/O 2I/O 3

D0

DQ4DQ5DQ6DQ7

DM1/DQS10NC/DQS10

DQSI/O 0I/O 1I/O 2I/O 3

D9

DMDMDQSI/O 0I/O 1I/O 2I/O 3

D1

DQ12DQ13DQ14DQ15

DM2/DQS11I/O 0I/O 1I/O 2I/O 3

D10

DMDQSDMCSDQSDQS

DQS3I/O 0I/O 1I/O 2I/O 3

D2

DQ20DQ21DQ22DQ23

DM3/DQS12I/O 0I/O 1I/O 2I/O 3

D11

DMCSDQSDQSDMDQSDQ24DQ26DQ27DQS4DQS4

I/O 0I/O 1I/O 2I/O 3

D3

DQ28DQ29DQ30DQ31

DM4/DQS13NC/DQS13

I/O 0I/O 1I/O 2I/O 3

D12

DMDQSDMDQSDQS5I/O 0I/O 1I/O 2I/O 3

D4

DM5/DQS14I/O 0I/O 1I/O 2I/O 3

D13

DMDQSDMCSDQSDQS

DQ40DQ41DQ42DQ43DQS6I/O 0I/O 1I/O 2I/O 3

D5

DQ44DQ45DQ46DQ47

DM6/DQS15I/O 0I/O 1I/O 2I/O 3

D14

Serial PD

SCL

SDA

WPA0

A1

A2

DMCSDQSDQSDMDQSDQ48DQ49DQ50DQ51DQS7DQS7

I/O 0I/O 1I/O 2I/O 3

D6

DQ52DQ53DQ54DQ55

DM7DQS16NC/DQS16

I/O 0I/O 1I/O 2I/O 3

D15

SA0SA1SA2

DMDQSDMDQSDQ56DQ57DQ58DQ59DQS8I/O 0I/O 1I/O 2I/O 3

D7

DM8/DQS17I/O 0I/O 1I/O 2I/O 3

VDDSPDVDD/VDDQVREF

Serial PDD0 - D17D0 - D17D0 - D17

D16

DMDQSDMCSDQSDQS

CB0CB1CB2CB3I/O 0I/O 1I/O 2I/O 3

D8

CB4CB5CB6CB7I/O 0I/O 1I/O 2I/O 3

VSS

D17

Signals for Address and Command Parity Function (M393T6450FZA)

S0*

BA0-BA1A0-A12RASCASWECKE0ODT0PCK7**

PCK7**

1:2REGISTER

RST

RSO-> CS : DDR2 SDRAMs D0-D17

RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17RA0-RA12 -> A0-A12 : DDR2 SDRAMs D0-D17RRAS -> RAS : DDR2 SDRAMs D0-D17RCAS -> CAS : DDR2 SDRAMs D0-D17RWE -> WE : DDR2 SDRAMs D0-D17RCKE0 -> CKE : DDR2 SDRAMs D0-D17RODT0 -> ODT0 : DDR2 SDRAMs D0-D17Notes :

1. DQ-to-I/O wiring may be changed per nibble.

2. Unless otherwise noted, resister values are 22 Ohms.

VSSVDD

PAR_IN100K ohms

C0C1

Register A

PPOVDDVDD

C0C1

Register B

PPOQERR

Err_Out

PAR_INPAR_IN

The resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: "Register Options for Unused Address inputs"

CK0

CSR of register 1 and DCS of register 2 connects to VDD.* RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.

CK0RESET

PLL

OE

PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8PCK7 -> CK : RegisterPCK7 -> CK : Register