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256MB, 512MB Registered DIMMs

240 Pin DDR2 Registered DIMM Clock Topology

DDR2 SDRAM

0ns (nominal)

PLL

DDR2 SDRAM

OUT1

120 ohms

CK0

120 ohms

IN

CK0

DDR2 SDRAM

Reg.A

120 ohmsC

Feedback In

Feedback Out

Reg.B

OUTN

120 ohms

Note:1.2.3.4.

The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal). Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.

Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.