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256MB, 512MB Registered DIMMs

Electrical Characteristics & AC Timing for DDR2-667/533/400 SDRAM

(0 °CASE °C; VDDQDDDDR2 SDRAM

Refresh Parameters by Device Density

Parameter

Refresh to active/Refresh command timeAverage periodic refresh interval

tRFCtREFI

0 °C ≤ TCASE ≤ 85°C85 °C < TCASE ≤ 95°CSymbol

256Mb757.83.9

512Mb1057.83.9

1Gb127.57.83.9

2Gb1957.83.9

4Gbtbd7.83.9

Unitsnsµsµs

Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

Speed

Bin (CL - tRCD - tRP)

ParametertCK, CL=3tCK, CL=4tCK, CL=5tRCDtRPtRCtRAS

min53.75315155439

70000

DDR2-667(E6)

5 - 5 - 5

max888

min53.75-15155540

70000

DDR2-533(D5)

4 - 4 - 4

max88-min55-15155540

70000

DDR2-400(CC)

3 - 3 - 3

max88-nsnsnsnsnsnsnsUnits

Timing Parameters by Speed Grade

(Refer to notes for informations related to this table at the bottom)

Parameter

DQ output access time from CK/CKDQS output access time from CK/CKCK high-level widthCK low-level widthCK half periodClock cycle time, CL=xDQ and DM input hold timeDQ and DM input setup time

Control & Address input pulse width for each input

DQ and DM input pulse width for each inputData-out high-impedance time from CK/CKDQS low-impedance time from CK/CKDQS-DQ skew for DQS and associated DQ signals

DQ hold skew factor

DQ/DQS output hold time from DQS

Write command to first DQS latching transitionDQS input high pulse width

Symbol

tACtDQSCKtCHtCLtHPtCKtDHtDStIPWtDIPWtHZtLZ(DQS)tLZ(DQ)tDQSQtQHStQHtDQSStDQSH

DDR2-667min

-450-4000.450.45min(tCL, tCH)

3000175500.60.35xtAC min2*tAC min

xxtHP - tQHSWL-0.250.35

DDR2-533min

-500-4500.450.45min(tCL, tCH)

37502251000.60.35xtAC min2*tACmin

xxtHP - tQHSWL-0.250.35

DDR2-400min

-600-5000.450.45min(tCL, tCH)

50002751500.60.35xtAC min2*tACmin

xxtHP - tQHSWL-0.250.35

UnitsNotes

pspstCKtCKpspspspstCKtCKpspspspspspstCKtCK

max

+450+4000.550.55x8000xxxxtAC maxtAC maxtAC max250350xWL+0.25

x

max

+500+4500.550.55x8000xxxxtAC maxtAC maxtAC max300400xWL+0.25

x

max

+600+5000.550.55x8000xxxxtAC maxtAC maxtAC max350450xWL+0.25

x