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256MB, 512MB Registered DIMMs

Input/Output Functional Description

SymbolCK0CK0CKE0~CKE1

TypeInputInputInput

Function

DDR2 SDRAM

Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.

Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.

Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is dis-abled, new commands are ignored but previous operations continue.

These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high.

I/O bus impedance control signals.

When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM.

Reference voltage for SSTL_18 inputs

Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunitySelects which SDRAM bank of four is activated.

During a Bank Activate command cycle, Address defines the row address.

During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is

selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to pre-charge.

Data and Check Bit Input/Output pins

Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once the write command is registered into the SDRAM.

Power and ground for the DDR SDRAM input buffers and core logicPositive line of the differential data strobe for input and output data.Negative line of the differential data strobe for input and output data.

These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range.This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDDSPD to act as a pullup.

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD to act as a pullup.

Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to 3.6 Volt operation).

The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-nized with the input clock )

Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)Parity error found in the Address and Control bus

Used by memory bus analysis tools (unused on memory DIMMs)

S0~S1

Input

ODT0~ODT1VREFVDDQBA0~BA1

InputInputSupplySupplyInput

A0~A9,A10/APA11~A12

Input

DQ0~63,CB0~CB7DM0~DM8VDD, VSSDQS0~DQS17DQS0~DQS17SA0~SA2SDASCLVDDSPDRESETPar_InErr_OutTEST

In/OutInputSupplyIn/OutIn/OutInputIn/OutInputSupplyInputInputInputIn/Out