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256MB, 512MB Registered DIMMs

Pin Configurations (Front side/Back side)

Pin

123456789101112131415161718192021222324252627282930

DDR2 SDRAM

Pin

616263646566676869707172737475767778798081828384858687888990

Front

VREFVSSDQ0DQ1VSSDQS0DQS0VSSDQ2DQ3VSSDQ8DQ9VSSDQS1VSSNCVSSDQ10DQ11VSSDQ16DQ17VSSDQS2DQS2VSSDQ18

Pin

121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150

Back

VSSDQ4DQ5VSSDM0/DQS9NC/DQS9VSSDQ6DQ7VSSDQ12DQ13VSSDM1/DQS10VSSRFURFUVSSDQ14DQ15VSSDQ20DQ21VSSDM2/DQS11NC/DQS11

VSSDQ22DQ23

Pin

313233343536373839404142434445464748495051525354555657585960

Front

DQ19VSSDQ24DQ25VSSDQS3DQS3VSSDQ26DQ27VSSCB0CB1VSSDQS8VSSCB2CB3VSSVDDQCKE0VDDNCNC/Err_OutVDDQA11A7VDDA5

Pin

151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180

Back

VSSDQ28DQ29VSSDM3/DQS12NC/DQS12

VSSDQ30DQ31VSSCB4CB5VSSDM8/DQS17VSSCB6CB7VSSVDDQCKE14VDDNCNCVDDQA12A9VDDA8A6

Front

A4VDDQA2VDD

Pin

181182183184KEY

185186187188189190191192193194195196197198199200201202203204205206207208209210

Back

VDDQA3A1VDDCK0VDDA0VDDBA1VDDQRASS0VDDQODT0NCVDDVSSDQ36DQ37VSSDM4/DQS13NC/DQS13

VSSDQ38DQ39VSSDQ44DQ45VSS

Pin

919293949596979899100101102103104105106107108109110111112113114115116117118119120

Front

VSSDQS5VSSDQ42DQ43VSSDQ48DQ49VSSSA2NC(TEST)VSSDQS6DQS6VSSDQ50DQ51VSSDQ56DQ57VSSDQS7DQS7VSSDQ58DQ59VSSSDASCL

Pin

211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240

Back

DM5/DQS14VSSDQ46DQ47VSSDQ52DQ53VSSRFURFUVSSDM6/DQS15NC/DQS15

VSSDQ54DQ55VSSDQ60DQ61VSSDM7/DQS16NC/DQS16

VSSDQ62DQ63VSSVDDSPDSA0SA1

VSSVSSVDDNC/Par_InVDDA10/APBA0VDDQWEVDDQ4

ODT1VDDQVSSDQ32DQ33VSSDQS4DQS4VSSDQ34DQ35VSSDQ40DQ41

NC = No Connect, RFU = Reserved for Future Use

1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.

2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.4. CKE1,S1 Pin is used for double side Registered DIMM.

Pin Description

Pin NameCK0CK0CKE0, CKE1RASCASWES0, S1

A0~A9, A11~A12A10/APBA0, BA1SCL SDASA0~SA2Par_InErr_OutRESET

Description

Clock Inputs, positive lineClock inputs, negative lineClock EnablesRow Address StrobeColumn Address StrobeWrite EnableChip SelectsAddress Inputs

Address Input/AutoprechargeDDR2 SDRAM Bank Address

Serial Presence Detect (SPD) Clock InputSPD Data Input/OutputSPD address

Parity bit for the Address and Control busRegister and PLL control pin

Pin Name ODT0~ODT1 DQ0~DQ63CB0~CB7DQS0~DQS8DQS0~DQS8DM(0~8),DQS(9~17) DQS9~DQS17RFUNCTEST

DescriptionOn die terminationData Input/Output

Data check bits Input/OutputData strobes

Data strobes, negative lineData Masks / Data strobes (Read)Data strobes (Read), negative lineReserved for Future Use No Connect

Memory bus test tool

(Not Connect and Not Useable on DIMMs)

PowerVDDPowerVDDQVSSVREF

Ground

Input/Output ReferenceSPD Power

Parity error found in the Address and Control busVDDSPD

* The VDD and VDDQ pins are tied to the single power-plane on PCB.