IS61LPD102418A-200TQ中文资料(8)

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IS61VPD51236A,IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A

TRUTH TABLE(1-8)(3CE option)

OPERATION

Deselect Cycle, Power-DownDeselect Cycle, Power-DownDeselect Cycle, Power-DownDeselect Cycle, Power-DownDeselect Cycle, Power-DownSnooze Mode, Power-DownRead Cycle, Begin BurstRead Cycle, Begin BurstWrite Cycle, Begin BurstRead Cycle, Begin BurstRead Cycle, Begin BurstRead Cycle, Continue BurstRead Cycle, Continue BurstRead Cycle, Continue BurstRead Cycle, Continue BurstWrite Cycle, Continue BurstWrite Cycle, Continue BurstRead Cycle, Suspend BurstRead Cycle, Suspend BurstRead Cycle, Suspend BurstRead Cycle, Suspend BurstWrite Cycle, Suspend BurstWrite Cycle, Suspend Burst

ADDRESSNoneNoneNoneNoneNoneNoneExternalExternalExternalExternalExternalNextNextNextNextNextNextCurrentCurrentCurrentCurrentCurrentCurrent

CEHLLLLXLLLLLXXHHXHXXHHXH

CE2XXHXHXLLLLLXXXXXXXXXXXX

CE2XLXLXXHHHHHXXXXXXXXXXXX

ZZLLLLLHLLLLLLLLLLLLLLLLL

ADSPADSCXLLHHXLLHHHHHXXHXHHXXHX

LXXLLXXXLLLHHHHHHHHHHHH

ADVWRITEXXXXXXXXXXXLLLLLLHHHHHH

XXXXXXXXLHHHHHHLLHHHHLL

OEXXXXXXLHXLHLHLHXXLHLHXX

ISSI

CLKL-HL-HL-HL-HL-HXL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-H

DQ

®

High-ZHigh-ZHigh-ZHigh-ZHigh-ZHigh-ZQHigh-ZDQHigh-ZQHigh-ZQHigh-ZDDQHigh-ZQHigh-ZDD

NOTE:

1.X means “Don’t Care.” H means logic HIGH. L means logic LOW.

2.For WRITE, L means one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GW is LOW.WRITE = H for all BWx, BWE, GW HIGH.

3.BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’sandDQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions.DQPc andDQPd are only available on the x36 version.

4.All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.5.Wait states are inserted by suspending burst.

6.For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during theinput data hold time.

7.This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

8.ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte writeenable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.

8Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev.B02/03/06