IS61LPD102418A-200TQ中文资料(7)

元器件交易网

IS61VPD51236A, IS61VPD102418A, IS61LPD51236A, IS61LPD102418A

PIN CONFIGURATION

100-PIN TQFP

ISSI

®

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. Thesepins must tied to the two LSBs of theaddress bus.

Synchronous Address InputsSynchronous Controller Address StatusSynchronous Processor Address StatusSynchronous Burst Address AdvanceSynchronous Byte Write EnableSynchronous Byte Write EnableSynchronous Clock

Synchronous Data Input/Output

7

DQPa-DQPbGWMODEOEVDDVDDQVssZZ

Parity Data I/O; DQPa is parity forDQa1-8; DQPb is parity for DQb1-8Synchronous Global Write EnableBurst Sequence Mode SelectionOutput Enable

3.3V/2.5V Power SupplyIsolated Output Buffer Supply:3.3V/2.5VGroundSnooze Enable

AADSCADSPADVBWa-BWbBWECLKDQa-DQb

CE, CE2, CE2Synchronous Chip Enable

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev.B02/03/06