IS61LPD102418A-200TQ中文资料(6)

元器件交易网

IS61VPD51236A,IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A

PIN CONFIGURATION

100-PIN TQFP

ISSI

®

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. Thesepins must tied to the two LSBs of theaddress bus.

Synchronous Address InputsSynchronous Controller Address StatusSynchronous Processor Address StatusSynchronous Burst Address AdvanceSynchronous Byte Write EnableSynchronous Byte Write EnableSynchronous Chip EnableSynchronous Chip EnableSynchronous Clock

DQa-DQdDQPa-DQPdGWMODEOEVDDVDDQVssZZ

Synchronous Data Input/OutputParity Data Input/Output

Synchronous Global Write EnableBurst Sequence Mode SelectionOutput Enable

3.3V/2.5V Power SupplyIsolated Output Buffer Supply:3.3V/2.5VGroundSnooze Enable

AADSCADSPADVBWa-BWdBWECE, CE2CE2CLK6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev.B02/03/06