Verdi_HWSW_Debug_Customer_Presentation(4)

Verdi 教程

HW/SW DebugEmbedded Processor Debug with Synchronized RTL, C, Assembly Enables co-debug between RTL and SW HW and SW debug synchronized in time View C/Assembly source, C variables, stack Debugs multiple core simultaneously Supports ARM A5, A7, A8, A9, A15, M3 Easy to support additional coresCPU (RTL) Mem Model Mem Image Programmer’s ViewX-Bar (RTL)USB Host IIPApplication Logic (RTL)SoC SimulationFull Verdi Features© Synopsys 20134Confidential