Verdi_HWSW_Debug_Customer_Presentation(17)

Verdi 教程

Recorder Modules – XMR/Logic BasedSimulation Recorder Module FSDB Recorder instance extracts the information based on XMRs (cross module references) and logic codeHW/SW Debug`define CPU_top minitb.cpu_inst reg [31:0] pc; wire[31:0] core_regs[0:14]; wire CLK; wire [31:1] ETMIA; wire [25:0] ETMICTL; … (more definitions here) assign core_regs[0] = `CPU_top.uix.regfile.reg00; …assign CLK=`CPU_top.uix.ck_gclkc; assign ETMICTL = `CPU_top.uix.ETMICTL; assign ETMIA = { `CPU_top.uix.ETMIA, 1'b0 }; … (more assignments here) always @(ETMIA or ETMICTL) begin if (ETMICTL[0]) pc = ETMIA; else pc = {32{1'bx}}; endSynopsys Confidential© Synopsys 201317