Verdi_HWSW_Debug_Customer_Presentation(10)

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HW/SW ModularizationDATA GATHERING Core register Program counter Flag register (CPSR, …) DATA STORING Record data for non-linear access in interactive and post process flows 10x smaller in fsdb ENGINE Communicate with gdb Access data VIZUALIZATION SW debug HW debug HW/SW debug syncVerilog recorder modules ARM TARMAC (RTL and ISS) Custom Cores XMR Log-Filegdbcore targetedSW debugEclipse CDTFSDB HW-SW Core HW debugVerdiVerdi Platform© Synopsys 201310Synopsys Confidential