Verdi_HWSW_Debug_Customer_Presentation(3)

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SoC Debug ChallengesNeed a Programmers view of the CPUCPU Software Debug Encrypted Model ? Registers + Nets ? No or Low-Visibility Looks like a Black Box Need Software DebuggerUSB VIP CPU (RTL) SoC Simulation CPU (RTL) Memory Model Memory Image arm-gcc C CodeInterconnect Fabric User Block (C/DPI) User Logic (RTL)USB IIPProtocol Analyzer VIP Debug© Synopsys 2013 3Verdi Debug C (PLI & DPI)Synopsys ConfidentialVerdi Debug RTL, Testbench