Verdi_HWSW_Debug_Customer_Presentation(12)

Verdi 教程

HW/SW-Accel : ISS/Fast Model CoresAccurate RTL SimulationTradeoffFast ISS + RTL SimulationARM RTL (Verilog)ARM RTL (Verilog) Soc FabricARM FM (C / ISS)TLM TransactorARM FM (C / ISS)TLM TransactorSoc Fabric Mem/Denali/… Memory BackdoorMem/Denali/…SocSoc RTL Core Solution– – – RTL or DSM Model TARMAC based (ARM cores) Log or XMR based (non ARM cores) ISS Core Solution– – – Replace RTL or DSM with ISS Model DW-VIP Models for AXI/Fabric BFM’s ISS runs faster than RTL, faster performance Accurate Simulation– – Real RTL, cycle accurate RTL Speed, not suitable for OS boot Faster Simulation– – – Memory Access via Backdoor or Fabric Backdoor allows boot of OS Access peripherals via fabric as needed© Synopsys 201312Synopsys Confidential