课程设计报告---四人抢答器(10)

器件生成所使用的VHDL语言：

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ch41a is

Port(d1 : in std_logic; d2 : in std_logic; d3 : in std_logic; d4 : in std_logic;

q : out std_logic_vector(3 downto 0)); end ch41a;

architecture Behavioral of ch41a is begin

process(d1,d2,d3,d4)

variable tmp:std_logic_vector(3 downto 0); begin

tmp:=d1&d2&d3&d4; case tmp is

when "0111"=>q<="0001"; when "1011"=>q<="0010"; when "1101"=>q<="0010"; when "1110"=>q<="0100"; when others=>q<="1111"; end case; end process; end Behavioral;

器件描述：

该器件主要实现d1~d4输入的转换功能，也就是将最原始的抢答输入进行转换，通过该器件，将原始抢答时刻s1~s4状态输出至发光二极管，也就最终实现谁先抢答，对应的发光二极管点亮。 (4). Count 元件

器件生成所使用的VHDL语言：

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity count is

Port(clk : in std_logic; en : in std_logic;

h : out std_logic_vector(3 downto 0); l : out std_logic_vector(3 downto 0); sound : out std_logic); end count;

architecture Behavioral of count is begin

process(clk,en)

variable hh,ll:std_logic_vector(3 downto 0); begin

if clk'event and clk='1' then if en='1' then

if ll=0 and hh=0 then sound<='1'; elsif ll=0 then ll:="1001"; hh:=hh-1; else