+ncno_sdfa_header Do not print the SDF annotation header

+ncno_tchk_xgen Turn off X-generation in VITAL timing checks +ncno_vpd_msg Turn off VITAL pathdelay warnings

+ncno_vpd_xgen Turn off X-generation in VITAL pathdelays +ncnobinding+ Skip instances of unit given as argument

+ncnobuiltin Do not use any built-in IEEE operators

+ncnocifcheck Disables constraint checking in VDA functions +ncnocopyright Suppress printing of copyright banner

+ncnodeadcode Turn off dead code optimization

+ncnoesp Disable edge-sensitive iopath delays

+ncnoipd Ignore interconnect delays

+ncnokey Suppress generation of the default keyfile

+ncnolicpromote Do not use a mixed language license

+ncnolicsuspend Disable suspending licenses for SIGTSTP

+ncnoline Do not locate source line on errors

+ncnolog Suppress generation of the default logfile

+ncnomempack Do not pack memories

+ncnomxindr Do not generate NOMXINDR error; split net instead +ncnontcglitch Suppress delayed net glitch suppression message +ncnoparamerr Do not flag setting undefined parameters as error +ncnopragmawarn Disable pragma related warning messages. +ncnoscynceverydelta Turn Delta cycle accuracy off

+ncnosncomp Do not compile Specman input files

+ncnosource Do not check source file timestamps in update +ncnospecview Do not invoke the Specview GUI

+ncnostdout Turn off output to screen (terminal)

+ncnotimezeroasrtmsg Suppress printing of time zero assert messages +ncnovitalaccl Turn off VITAL acceleration

+ncnovitalcheck Suppress VITAL compliance checking

+ncnowarn+<arg> Disable printing of the specified warning

+ncnoxilinxaccl Turn off Xilinx acceleration

+ncntc_level+<level> Select NTC algorithm 1 or 2 (default is 2)

+ncntc_verbose Display verbose information about NTC process +ncntcnotchks Generate NTC delay while removing timing checks +nco_ext+<ext> Override extensions for object files

+ncomicheckinglevel+<level> Specify OMI checking level {Min, Std, Max} +ncoverride_precision Override the timescale precision in Verilog

+ncoverride_timescale Override the timescale directives in Verilog

+ncpassword Prompt for sim passwd for SimVis walkup connect +ncpli_export Export symbols from loadpli, loadvpi

+ncpliverbose Print information for PLI/VPI task registration +ncppdb+<dbase> Invoke the post-processing environment

+ncppe Enter post-processing mode

+ncpragma Enable pragma processing