+multisource_int_delays Make interconnect timing be multisource capable +name+<name> Generate snapshot with specified name

-native Use the native C and C++ compiler

+nc64bit Invoke 64bit version

+nca_ext+<ext> Override extensions for archive files

+ncafile+<file> Specify an access file to be used

+ncams Force Verilog-AMS and VHDL-AMS compilation +ncamsfastspice Enable Fast SPICE simulator (UltraSim)

+ncamslic Check out an AMS license

+ncamspartinfo+<file>

+ncamsv_ext+<ext>

+ncanalogcontrol+<arg>

+ncanno_simtime

+ncappend_log

-ncb_environment <arg>

-ncb_file <arg>

-ncb_filter <arg>

-ncb_format <arg>

-ncb_nodefaultenv

-ncb_order <arg>

-ncb_report <arg>

-ncb_sortby <arg>

+ncbatch

+ncbinding+

+ncc_ext+<ext>

+ncccargs

+nccd_lexpragma

+nccds_implicit_tmpdir+

+nccds_implicit_tmponly

+nccdslib+<arg>

+ncchecktasks

+ncchkdigdisp

+ncconffile+<file_name>

+ncconfflat

+ncconfhier

+ncconfname+<arg>

+nccontrolrelax+<arg>

+nccovdesign+<string>

+nccovdut+<string>

+nccoverage+<string>

+nccovfile+<file>

+nccovnomodeldump

+nccovoverwrite

+nccovtest+<string> Mixed-signal partition information Override extensions for Verilog-AMS sources Specify analog simulation control file Enable delay annotation at simulation time Append output log to existing log Specify environment file to be loaded by Ncbrowse File for Ncbrowse to load command line arguments Filter for report generation by Ncbrowse Set the format of messages in the report Prevent Ncbrowse from using default environment Set the order in which items are shown Specify the report file to be created by Ncbrowse Specify a sort order to Ncbrowse for report Run simulation in batch mode, this is the default Force explicit submodule or unit L.C:v binding Override extensions for C sources Pass arguments to the C compiler Process preprocessor directive before lex pragmas Specify location for design data storage Force tools to read design data only from tmpdir Specify a cds.lib file to be used Check that all $tasks are built-in system tasks Perform digital net's discipline compatibility Generate a configuration file with the given name Requires -CONFFILE, generate a VHDL flat config Requires -CONFFILE, gen VHDL hierarchical config Requires -CONFFILE, specify output config name Enable specific relaxed VHDL interpretation Select coverage design name Select DUT for Coverage Enable coverage instrumentation Specify coverage instrumentation control file Disable coverage design database (model) dumping Enable overwrite of coverage output files Select coverage test name