+ncintermod_path Make interconnects be multisource capable

+nclexpragma Enable lexical pragma processing

+nclib_binding Defaults back to the IUS5.4 binding search order +nclibcell Mark all cells with `celldefine

+nclibdirname+<dir> Specify directory name to store created library

+nclibdirpath+<path> Relative path where libraries should be created

+nclibmap+<arg> Specify the library mapping file

+nclibname+<name> Specify the name of a library to search

+nclicq Queue simulation till license is available

+nclinedebug Enable line debugging capabilities

+nclist Produce a VHDL source listing in specified file +nclog_ncelab+<logfile> Place the ncelab output into specified logfile

+nclog_ncsc_run+<logfile> Place the ncsc_run output into specified logfile

+nclog_ncsim+<logfile> Place the ncsim output into the specified logfile +nclog_ncvhdl+<logfile> Place the ncvhdl output into specified logfile

+nclog_ncvlog+<logfile> Place the ncvlog output into specified logfile

+nclog_svpp+<logfile> Place the svpp output into specified logfile

+nclps_assign_ft_buf Disable continuous assignment as feed through net +nclps_cpf+<file> Specify a CPF file for low power simulation

+nclps_iso_off Turn off port isolation

+nclps_logfile+<logfile> Specify a log file for low power simulation

+nclps_off Turn off low power simulation

+nclps_rtn_lock Lock the retained reg value

+nclps_rtn_off Turn off state retention

+nclps_simctrl_on Enable runtime control over low power simulation +nclps_stime+<time> Specify a time to start low power simulation

+nclps_stl_off Turn off state loss

+nclps_verbose+<level> Specify a level of information reporting

+nclps_verify Enables automatic Low Power verification

+nclps_vhdlpwron Brings back VHDL objects to a defined state

+ncls_all Run ncls with the -all option

+ncls_dep Run ncls with the -dep option

+ncls_so Run ncls with the -source option

+ncls_ss Run ncls with the -snapshot option

+ncmakelib+<libpath[:logical]> Compile HDL files into specified library

+ncmatchinst+<instance> Specify name of instance to match for -INSERT +ncmaxdelays Select maximum delays for simulation

+ncmindelays Select minimum delays for simulation

+ncmodelincdir+<dirlist> Specify a list of directories separated by :

+ncmodelpath+<string> For Verilog-AMS, specify list of source files

+ncmultview Allows selection of arch/config for binding

+ncnamemap_mixgen Do name mapping from VHDL generics to Vlog params +ncno_cross_def_bind Suppress cross-language default binding

+ncno_notifier Ignore notifiers in timing checks