-sa_force_list <arg> Provide the input file to force the modules

-sc_main Run with an sc_main entry point

+scAllowSCFromPLI Allow SystemC from PLI

-scautoshell SYSTEMC|HDL|VERILOG|VHDL Automatically generate shell modules +scConvertWarn Turn on X/Z -> 0 data conversion warnings

+scDisableDynamicHierarchy Disable Dynamic Hierarchy in designs with SystemC +scgafap+<args> Either +on +off or +auto

+scNoDestructorsInElab Do not run desctructors during elaboration

+sctop+<top> Specify SystemC module name to be the top level -scv Turn on linking of the CVE and SCV libraries +sdf_file+<arg> Specify the SDF annotation file

+sdf_nopulse Ignore SDF pulse information

+sdf_specpp Use PATHPULSE parameters in specify block -seed <seed> Set the seed for value

+show_cancelled_e Filter canceled events (negative pulses) to e +show_forces Turn on support for force -show

-showtoptype Show the type of the top level design unit

+simvisargs+<string> Quoted string of SimVision command-line arguments -snheader <fileName> Have specman create a header file

+snheaderargs+<string> Pass arguments to snheader generation phase -snrebuild Force the recompilation of the e input files

-spec <specfile> Specify an alternative spec file

-spice_ext <ext> Override extensions for SPICE sources

-stats Print counts of the error/warning messages issued +sv Force SystemVerilog compilation

+sv_lib=<lib> Dynamically load a DPI library

+sv_root+<path> Specify root path for "sv_lib" switch

+svperf+<up> Enable SystemVerilog UniquePriority performance -svpp Allow svpp to preprocess verilog files

-svppargs <string> Pass arguments to svpp

-svpptestcase <tarfile> Tar and zip the svpp simulation

+svrnc=<option> Set SystemVerilog constraints options

+sysc SystemC is present

+systemc_args+<args> List of arguments to sc_main

+systemverilog_ext+<ext> Override extensions for SystemVerilog sources -testcoverage <arg> Enable Logic Depth calculation

-timeunit_case Prints time units from std.textio in upper case -topic <category|option> Lists all ncsc_run option in a group or more info +transport_int_delays Make interconnect timing be multisource capable -u Convert identifiers to uppercase

-urm Add search directories needed by the URM library -urmhome <path> Override the default location of the URM library -v <file> Specify a library file to be used

+v1995 Turn off new Verilog-2001 keywords