Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

3ExperimentalApproach

Thissectionoutlinestheapproachtothereportedexperiments.Thesimula-tionstrategyisexplained,followedbysomedetailofsimulationparameters;inconclusion,expected ndingsarediscussed.

3.1SimulationStrategy

Arangeofvariationsonastandard2-levelhierarchyiscomparedtosimilarvariationsonRAMpage,withandwithoutcontextswitchesonmisses.RAMpagewithoutcontextswitchesonmissestoconveysthee ectsofaddingassociativity(withanoperatingsystem-stylereplacementstrategy).AddingcontextswitchesonmissesshowsthevalueofalternativeworkonamisstoDRAM.Simulationsaretrace-driven,anddonotmodelthepipeline.ProcessorspeedisinGHz,representinginstructionissueratewithoutmisses,notclockspeed.

Ignoringthepipelinelevelneglectse ectslikebranchesandthepotentialforotherimprovementslikenon-blockingcaches.However,theresultsbeinglookedforherearerelativelylargeimprovements,soinaccuraciesofthiskindareunlikelytobesigni cant.Whatisimportantisthee ectastheCPU-DRAMspeedgapincreases,andthesimulationisofsu cientaccuracytocapturesuche ects,ashasbeendemonstratedinpreviouswork.

3.2SimulationParameters

Parametersaresimilartopreviouspublishedworktomakeresultscomparable.ThefollowingparametersarecommonacrossRAMpageandtheconventionalhierarchy.ThisrepresentsthebaselinebeforenewL1andTLBvariations:–L1cache–16Kbyteseachofdataandinstructioncache,physicallytaggedandindexed,direct-mapped,32-byteblocksize,1-cyclereadhit,12-cyclepenaltyformissestoL2(orRAMpageSRAMmainmemory);fordatacache:perfectwritebu ering(zeroe ectivehittime),writeback(12-cyclepenalty;9cyclesforRAMpage:noL2tagtoupdate),writeallocateonmiss–TLB–64entries,fullyassociative,randomreplacement

–DRAMlevel–DirectRambus[8]withoutpipelining:50nsbefore rstrefer-encestarted,thereafter2bytesevery1.25ns–pagingofDRAM–invertedpagetable:sameorganizationasRAMpagemainmemoryforsimplicity,in niteDRAMwithnomissestodisk–TLBandL1datahitsfullypipelined–onlytimeforL1dorTLBreplace-mentsormaintaininginclusioncostedas“hits”

Thesamememorytimingisusedasinearliersimulations.AlthoughfasterDRAMhassincebecomeavailable,thetimingcanbeseenasrelativetoapar-ticularCPU-DRAMspeedgap,andthe gurescanaccordinglyberescaled.Contextswitchesaremodelledbyinterleavingatraceoftext-bookcode.Acontextswitchistakenevery500,000references,thoughRAMpagewithcontextswitchesonmissesalsotakesacontextswitchonamisstoDRAM.TLBmissesarehandledbyatraceofpagetablelookupcode,withvariationsontimeforalookupbasedonprobablevariationsinprobesintoaninvertedpagetable[22].