Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

ofthestandardhierarchy.RAMpageTLBmissesdonotresultinreferencestoDRAM,unlessthereisapagefault,sotheadditionalreferencesshouldnotresultinasimilarlysubstantialperformancehit.

Fig.6illustratesexecutiontimesforthehierarchiesat1and8GHz,thespeedgapwhichshowso di erencesmostclearly.Therearetwocompetinge ects:asL2block(SRAMpagesize)increases,misspenaltytoDRAMincreases.InRAMpage,reducedTLBmissescompensateforthehigherDRAMmisspenalty,buttheperformanceofthestandardhierarchybecomesworseasblocksizein-creases.TLBsizevariationmakeslittledi erencetoperformanceofthestandardhierarchywiththesimulatedworkload.PerformanceofRAMpagewithswitchesonmissesdoesnotvarymuchforpagesof512BandgreaterevenwithTLBvariations,whileRAMpagewithoutswitchesisbestwith1024Bpages.

Theperformance-optimalTLBandpagesizecombinationforRAMpagewithoutcontextswitchesonmisses,witha512entryTLB,isa1024Bpageforallissuerates.Inpreviouswork,witha64-entryTLB,theoptimalpagesizeat1GHzwas2048B,whileotherissueratesperformedbestwith1024Bpages.Thus,alargerTLBresultsinasmallerpagesizebeingoptimalforthe1GHzspeed.Whileotherpagesizesarestillslowerthanthe1024Bpagesize,forallcaseswithpagesof512BandgreaterRAMpagewithoutcontextswitchesonmissesisfasterthanthestandardhierarchy.

ForRAMpagewithcontextswitchesonmisses,theperformance-optimalpagesizehasshiftedto1024BwithalargerTLB.Previouslythebestpagesizewas4096Bfor1,2and4GHzand2048Bfor8GHz.ATLBof256oreven128entriescombinedwiththe1024Bpagewillyieldoptimumoralmostoptimumperformance.Witha1024Bpageand256entries,atotalof256KB,or6.25%oftheRAMpagemainmemoryismappedbytheTLB,whichappearstobesu cientforthisworkload(a4KBpagewitha512-entryTLBmapshalftheSRAMmainmemory,overkillforanyworkloadwithreasonablelocalityofrefer-ence).Nonetheless,TLBperformanceishighlydependentonapplicationcode,soresultspresentedhereneedtobeconsideredinthatlight.

Contrastingthe1Ghzand8GHzcasesin g.6makesitclearagainhowthedi erencesbetweenRAMpageandaconventionalhierarchyscaleastheCPU-DRAMspeedgapincreases.At1GHz,allvariationsarereasonablycomparableacrossarangeofparameters.At8GHz,RAMpageisclearlybetterinallvaria-tions,butevenmoresowithcontextswitchesonmisses.AlargerTLBbroadenstherangeofusefulRAMpagecon gurations,withoutsigni cantlyalteringthestandardhierarchy’scompetitiveness.

4.3Summary

Insummary,theRAMpagemodelwithcontextswitchesonmissesgainsmostfromL1cacheimprovements,thoughtheotherhierarchiesalsoreduceexecutiontime.However,withouttakingcontextswitchesonmisses,increasingthesizeofL1hasthee ectofincreasingthefractionoftimespentwaitingforDRAM,sincethenumberofDRAMreferencesisnotreduced,noristheirlatencyhidden.AswasshownbyscalinguptheCPU-DRAMspeedgap,onlyRAMpagewith