Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

speci ctoconventionalhierarchy

The“conventional”systemhasa2-wayassociative4MbyteL2.TheL2cacheanditsbustotheCPUtheareclockedatonethirdoftheCPUissuerate(thecycletimeisintendedtorepresentasuperscalarissuerate).TheL2cache-CPUbusis128bitswideandrunsHitsontheL2cachetake4cyclesincludingthetagcheckandtransfertoL1.InclusionbetweenL1andL2ismaintained[12].TheTLBcachesvirtualpagetranslationstoDRAMphysicalframes.speci ctoRAMpagehierarchy

InRAMpagesimulations,mostparametersremainthesame,exceptthattheTLBmapstheSRAMmainmemory,andfullassociativityisimplementedinsoftware,throughasoftwaremisshandler.TheOSkeeps6pagespinnedintheSRAMmainmemorywhensimulatinga4Kbyte-SRAMpage,i.e.,24Kbytes,whichincreasestoto5336pagesfora128byteblocksize,atotalof667Kbytes.inputsandvariations

TracesarefromtheTracebasetracearchiveatNewMexicoStateUniversity1.

1.1-billionreferencesareused,withtracesinterleavedtocreatethee ectofamultiprogrammingworkload.

TomeasurevariationsonL1caches,thesizeofeachoftheinstructionanddatacacheswasvariedfromtheoriginalsizeof16KBto32KB,64KB,128KBand256KB.Toexploremoreofthedesignspace,L1blocksizewasmeasuredatsizesof32,64and128bytes.WedidnotvaryL2blocksizeswhenvaryingL1:anoptimumsizewasdeterminedinpreviouswork[21,22].However,whilevaryingtheTLB,wedidvaryL2blocksizeintheconventionalhiearchy,forcomparisonwithvaryingtheRAMpageSRAMmainmemorypagesize.Tomeasurethee ectofincreasingtheTLBsize,wevarieditfromtheoriginal64entriesto128,256and512.EvenlargerTLBsexist(e.g.,Power4hasa1024-entryTLB[29]),butthisrangeissu cienttocapturevariationsofinterest.

3.3ExpectedFindings

AsL1becomeslarger,RAMpagewithoutcontextswitchesonmissesshouldseelessofagain.WhileimprovingL1shouldnota ecttimespentinDRAM,RAMpage’sextraoverheadsinmanagingDRAMmayhaveamoresigni cante ectonoverallruntime.However,asthefractionofreferencesinupperlevelsincreaseswithoutadecreaseinreferencestoDRAM,contextswitchesonmissesshouldbecomemorefavourable.

AstheTLBsizeincreases,weexpecttoseesmallerSRAMpagesizesbecomeviable.IftheTLBhas64entriesandthepagesizeis4KBwitha4MBSRAM