L1 Cache and TLB Enhancements to the RAMpage Memory Hierarch(14)

时间:2025-03-10

Abstract. The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main memory. This paper illustrates how more aggressive components higher

5.3OverallConclusion

RAMpagehasbeensimulatedinavarietyofforms.Inthislateststudy,en-hancingL1andtheTLBhaveshownthatitgainssigni cantlymorefromsuchimprovementsthanaconventionalarchitectureinsomecases.Themostimpor-tant ndinggenerallyfromRAMpageworkisthat ndingotherworkonamisstoDRAMisbecomingincreasinglyviable.WhileRAMpageisnottheonlyap-proachto ndingsuchalternativework,itisapotentialsolution.Ascomparedwithhardwaremultithreadingapproaches,itsmainadvantageisthe exibilityofasoftwaresolution,thoughthisneedstobecomparedtohardwaresolutionstoestablishtheperformancecostofextra exibility.

References

1.ThomasAlexanderandGershonKedem.Distributedprefetch-bu er/cachede-signforhigh-performancememorysystems.InProc.2ndIEEESymp.onHigh-PerformanceComputerArchitecture,pages254–263,SanJose,CA,February1996.

2.AMD.HyperTransporttechnology:Simplifyingsystemdesign[online].October2002./docs/26635A_HT_System_Design.pdf.

3.J.M.Borkenhagen,R.J.Eickemeyer,R.N.Kalla,andS.R.Kunkel.Amulti-threadedPowerPCprocessorforcommercialservers.IBMJ.ResearchandDevel-opment,44(6):885–898,November2000.

4.T.ChenandJ.Baer.Reducingmemorylatencyvianon-blockingandprefetchingcaches.InProc.5thInt.Conf.onArchitecturalSupportforProgrammingLan-guagesandOperatingSystems(ASPLOS-5),pages51–61,September1992.

5.T-F.Chen.Ane ectiveprogrammableprefetchengineforon-chipcaches.InProc.28thInt.Symp.onMicroarchitecture(MICRO-28),pages237–242,AnnArbor,MI,29November–1December1995.

6.D.R.Cheriton,H.A.Goosen,H.Holbrook,andP.Machanick.Restructuringaparallelsimulationtoimprovecachebehaviorinashared-memorymultiprocessor:Thevalueofdistributedsynchronization.InProc.7thWorkshoponParallelandDistributedSimulation,pages159–162,SanDiego,May1993.

7.D.R.Cheriton,G.Slavenburg,andP.Boyle.Software-controlledcachesintheVMPmultiprocessor.InProc.13thInt.Symp.onComputerArchitecture(ISCA’86),pages366–374,Tokyo,June1986.

8.R.Crisp.DirectRambustechnology:Thenewmainmemorystandard.IEEEMicro,17(6):18–28,November/December1997.

9.B.Davis,T.Mudge,B.Jacob,andV.Cuppu.DDR2andlowlatencyvariants.InSolvingtheMemoryWallProblemWorkshop,Vancouver,Canada,June2000.Inconjunctionwith26thAnnuallnt.Symp.onComputerArchitecture.

10.ErikG.HallnorandStevenK.Reinhardt.Afullyassociativesoftware-managed

cachedesign.InProc.27thAnnualInt.Symp.onComputerArchitecture,pages107–116,Vancouver,BC,2000.

11.J.Handy.TheCacheMemoryBook.AcademicPress,SanDiego,CA,2ed.,1998.

puterArchitecture:AQuantitativeAp-

proach.MorganKau mann,SanFrancisco,CA,2ed.,1996.

13.J.HuckandJ.Hays.Architecturalsupportfortranslationtablemanagementin

largeaddressspacemachines.InProc.20thInt.Symp.onComputerArchitecture(ISCA’93),pages39–50,SanDiego,CA,May1993.

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