DAC 芯片~ 16位超级好用,不容错过

POWER-ON RESET

The DAC8501 contains a power-on reset circuit that controlsthe output voltage during power-up. On power-up, the DACregister is filled with zeros and the output voltage is 0V; itremains there until a valid write sequence is made to theDAC. This is useful in applications where it is important toknow the state of the output of the DAC when it is in theprocess of powering up.

MICROPROCESSORINTERFACING

DAC8501 TO 8051 INTERFACE

Figure 6 shows a serial interface between the DAC8501 anda typical 8051-type microcontroller. The setup for the inter-face is as follows: TXD of the 8051 drives SCLK of theDAC8501, whereas RXD drives the serial data line of thepart. The SYNC signal is derived from a bit-programmablepin on the port, in this case, port line P3.3 is used. When datais to be transmitted to the DAC8501, P3.3 is taken LOW. The8051 transmits data only in 8-bit bytes; thus only eight fallingclock edges occur in the transmit cycle. To load data to theDAC, P3.3 is left LOW after the first eight bits are transmitted,and a second write cycle is initiated to transmit the secondbyte of data. P3.3 is taken HIGH following the completion ofthe third write cycle. The 8051 outputs the serial data in aformat which has the LSB first. The DAC8501 requires itsdata with the MSB as the first bit received, therefore the 8051transmit routine must take this into account, and mirror thedata as needed.

POWER-DOWN MODES

The DAC8501 supports four separate modes of operationwhich are programmable by setting two bits (PD1 and PD0)in the control register. Table I shows how the state of the bitscorresponds to the mode of operation of the device.

PD1 (DB17)

0—011

PD0 (DB16)

0—101

OPERATING MODENormal OperationPower-Down ModesOutput 1k to GNDOutput 100k to GNDHigh-Z

TABLE I. Modes of Operation for the DAC8501.

When both bits are set to 0, the part works normally with itstypical current consumption of 250µA at 5V; however, for thethree power-down modes, the supply current falls to 200nAat 5V (50nA at 3V). Not only does the supply current fall, butthe output stage is also internally switched from the output ofthe amplifier to a resistor network of known values, this hasthe advantage that the output impedance of the part is knownwhile the part is in power-down mode. There are threedifferent options: the output is connected internally to GNDthrough a 1k resistor; a 100k resistor; or it is left open-circuited (High-Z), Figure 5 shows the output stage.

FIGURE 6. DAC8501 to 80C51/80L51 Interface.

DAC8501 TO Microwire INTERFACE

Figure 7 shows an interface between the DAC8501 and anyMicrowire compatible device. Serial data is shifted out on thefalling edge of the serial clock and is clocked into theDAC8501 on the rising edge of the SK signal.

FIGURE 5. Output Stage During Power-Down.

All linear circuitry is shut down when the power-down modeis activated, however, the contents of the DAC register areunaffected when in power-down. The time to exit power-down is typically 2.5µs for VDD = 5V, and 5µs for VDD = 3V,(see the Typical Characteristics for more information).

FIGURE 7. DAC8501 to Microwire Interface.

DAC8501

SBAS212A

13