DAC8501_芯片手册(12)

The output buffer amplifier is capable of generating rail-to-railvoltages on its output which gives an output range of0V to VDD; it is capable of driving a load of 2k in parallel with1000pF to GND. The source and sink capabilities of theoutput amplifier can be seen in the typical characteristics.The slew rate is 1V/µs with a full-scale settling time of 8µswith the output unloaded.

The inverting input of the output amplifier is brought out to theVFB pin which allows for better accuracy in critical applica-tions by tying the VFB point and the amplifier output togetherdirectly at the load. Other signal conditioning circuitry mayalso be connected between these points for specific applica-tions.

SERIAL INTERFACE

The DAC8501 has a 3-wire serial interface (, SCLK, andDIN), which is compatible with SPI, QSPI, and Microwire interfacestandards as well as most DSPs, (see the Serial Write Operationtiming diagram for an example of a typical write sequence).The write sequence begins by bringing the SYNC line LOW, datafrom the DIN line is clocked into the 24-bit shift register on thefalling edge of SCLK. The serial clock frequency can be as highas 30MHz, making the DAC8501 compatible with high-speedDSPs. On the 24th falling edge of the serial clock, the last databit is clocked in and the programmed function is executed (i.e., achange in DAC register contents and/or a change in the mode ofoperation).

At this point, the line can be kept LOW or brought HIGH.In either case, it must be brought HIGH for a minimum of 33nsbefore the next write sequence so that a falling edge of can initiate the next write sequence. As the buffer drawsmore current when the signal is HIGH than it does whenit is LOW, must be idled LOW between write sequencesfor lowest power operation of the part; as mentioned above, itmust be brought HIGH again just before the next write sequence.

MULTIPLYING MODE OPTIMIZATIONS

The DAC8501 is a version of the DAC8531 optimized formultiplying mode at a typical bandwidth of up to 350kHz,which gives better phase and gain performance.

Two aspects of the DAC8501 operation are affected by theoptimizations. The resistor string in the DAC8531 is discon-nected from the reference input when power-down mode isentered, but in the DAC8501, the resistor string continues todraw current from the reference input during power-downmode.

The DAC8501 has slightly different offset characteristicsfrom the DAC8531: the DAC8501 may output 0V for the firstfew hundred codes, whereas the DAC8531 typically has farfewer such dead codes near 0. Offset and gain errors aremeasured from code 0200H for both devices, so specifica-tions are not affected. In all other respects, the DAC8531 andDAC8501 operate identically.

Multiplying-mode bandwidth is measured at both small-signaland full-power levels. Bandwidth at full-power amplitude,which is typically 64kHz, is limited by the 1V/µs slew rate ofthe output amplifier. Small-amplitude signals that do notcause the amplifier to slew are bandlimited by the outputamplifier to approximately 350kHz. If the design approacheseither of these limits, the DAC8501 must be tested in theapplication to ensure that it meets the needed requirements.

INPUT SHIFT REGISTER

The input shift register is 24 bits wide, as shown inFigure 3. The first six bits are don’t cares. The next two bits (PD1and PD0) are control bits that control which mode of operation thepart is in (normal mode or any one of three power-down modes):there is a more complete description of the various modes in thePower-Down Modes section. The next 16 bits are the data bitswhich are transferred to the DAC register on the 24th falling edgeof SCLK.

SYNC INTERRUPT

In a normal write sequence, the line is kept LOW for atleast 24 falling edges of SCLK and the DAC is updated on the24th falling edge. However, if is brought HIGH before the24th falling edge, this acts as an interrupt to the write sequence.When this happens, the shift register is reset and the writesequence is seen as invalid. Neither an update of the DACregister contents or a change in the operating mode occurs, asshown in Figure 4.

DB0

DB23X

PD1

PD0D15

D14

D13

D12

D11

D10

FIGURE 3. Data Input Register.

24th Falling Edge

CLKSYNCDIN