IS61LPD51218A-250B3I中文资料(8)
发布时间：2021-06-07
元器件交易网
IS61VPD25636A,IS61VPD51218A, IS61LPD25636A, IS61LPD51218A
PIN CONFIGURATION
100-PIN TQFP (256K X 36)
ISSI
®
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. Thesepins must tied to the two LSBs of theaddress bus.
Synchronous Address InputsSynchronous Controller AddressStatus
Synchronous Processor AddressStatus
Synchronous Burst Address AdvanceSynchronous Byte Write EnableSynchronous Byte Write Enable
DQa-DQdDQPa-DQPdGWMODEOEVDDVDDQVssZZ
Synchronous Data Input/OutputParity Data Input/Output
Synchronous Global Write EnableBurst Sequence Mode SelectionOutput Enable
3.3V/2.5V Power SupplyIsolated Output Buffer Supply:3.3V/2.5VGroundSnooze Enable
AADSCADSPADVBWa-BWdBWE
CE, CE2, CE2Synchronous Chip EnableCLK
Synchronous Clock
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