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IS61VPD25636A IS61LPD25636AIS61VPD51218A IS61LPD51218A

256K x 36, 512K x 18

9 Mb SYNCHRONOUS PIPELINED,

DOUBLE CYCLE DESELECT STATIC RAM

ISSI

MAY 2005

®

FEATURES

Internal self-timed write cycle

Individual Byte Write Control and Global Write Clock controlled, registered address, data andcontrol Burst sequence control using MODE input Three chip enable option for simple depthexpansion and address pipelining Common data inputs and data outputs Auto Power-down during deselect Double cycle deselect

Snooze MODE for reduced-power standby JTAG Boundary Scan for PBGA package Power Supply

LPD: VDDDDQVPD: VDDDDQ JEDEC 100-Pin TQFP,

119-pin PBGA and 165-pin PBGA package

DESCRIPTION

TheISSI IS61LPD/VPD25636A and IS61LPD/VPD51218A

are high-speed, low-power synchronous static RAMs de-signed to provide burstable, high-performance memory forcommunication and networking applications. The IS61LPD/VPD25636A is organized as 262,144 words by 36 bits, andthe IS61LPD/VPD51218A is organized as 524,288 wordsby 18 bits. Fabricated with ISSI's advanced CMOS technol-ogy, the device integrates a 2-bit burst counter, high-speedSRAM core, and high-drive capability outputs into a singlemonolithic circuit. All synchronous inputs pass throughregisters controlled by a positive-edge-triggered singleclock input.

Write cycles are internally self-timed and are initiated by therising edge of the clock input. Write cycles can be one to fourbytes wide as controlled by the write control inputs.Separate byte enables allow individual bytes to be written.The byte write operation is performed by using the bytewrite enable (BWE) input combined with one or moreindividual byte write signals (BWx). In addition, GlobalWrite (GW) is available for writing all bytes at one time,regardless of the byte write controls.

Bursts can be initiated with either ADSP (Address StatusProcessor) or ADSC (Address Status Cache Controller)input pins. Subsequent burst addresses can be generatedinternally and controlled by the ADV (burst addressadvance) input pin.

The mode pin is used to select the burst sequence order,Linear burst is achieved when this pin is tied LOW.Interleave burst is achieved when this pin is tied HIGH orleft floating.

FAST ACCESS TIME

SymboltKQtKC

Parameter

Clock Access TimeCycle TimeFrequency

2502.64250

2003.15200

UnitsnsnsMHz

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabilityarising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on anypublished information and before placing orders for products.