元器件交易网

IS61VPD25636A,IS61VPD51218A, IS61LPD25636A, IS61LPD51218A

TRUTH TABLE(1-8)

OPERATION

Deselect Cycle, Power-DownDeselect Cycle, Power-DownDeselect Cycle, Power-DownDeselect Cycle, Power-DownDeselect Cycle, Power-DownSnooze Mode, Power-DownRead Cycle, Begin BurstRead Cycle, Begin BurstWrite Cycle, Begin BurstRead Cycle, Begin BurstRead Cycle, Begin BurstRead Cycle, Continue BurstRead Cycle, Continue BurstRead Cycle, Continue BurstRead Cycle, Continue BurstWrite Cycle, Continue BurstWrite Cycle, Continue BurstRead Cycle, Suspend BurstRead Cycle, Suspend BurstRead Cycle, Suspend BurstRead Cycle, Suspend BurstWrite Cycle, Suspend BurstWrite Cycle, Suspend Burst

ADDRESSNoneNoneNoneNoneNoneNoneExternalExternalExternalExternalExternalNextNextNextNextNextNextCurrentCurrentCurrentCurrentCurrentCurrent

CEHLLLLXLLLLLXXHHXHXXHHXH

CE2CE2XXHXHXLLLLLXXXXXXXXXXXX

XLXLXXHHHHHXXXXXXXXXXXX

ZZLLLLLHLLLLLLLLLLLLLLLLL

ADSPADSCADVXLLHHXLLHHHHHXXHXHHXXHX

LXXLLXXXLLLHHHHHHHHHHHH

XXXXXXXXXXXLLLLLLHHHHHH

WRITEOEXXXXXXXXLHHHHHHLLHHHHLL

XXXXXXLHXLHLHLHXXLHLHXX

ISSI

CLKL-HL-HL-HL-HL-HXL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-H

DQ

®

High-ZHigh-ZHigh-ZHigh-ZHigh-ZHigh-ZQHigh-ZDQHigh-ZQHigh-ZQHigh-ZDDQHigh-ZQHigh-ZDD

NOTE:

1.X means “Don’t Care.” H means logic HIGH. L means logic LOW.

2.For WRITE, L means one or more byte write enable signals (BWa-d) and BWE are LOW or GW is LOW. WRITE = H for allBWx, BWE, GW HIGH.

3.BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’sandDQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version.DQPa-DQPd areavailable on the x36 version.

4.All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.5.Wait states are inserted by suspending burst.

6.For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH duringthe input data hold time.

7.This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

8.ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more bytewrite enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram forclarification.

PARTIAL TRUTH TABLE

FunctionReadRead

Write Byte 1Write All BytesWrite All BytesGWHHHHL

BWEHLLLX

BWaXHLLX

BWbXHHLX

BWcXHHLX

BWdXHHLX