元器件交易网

IS61VPD25636A,IS61VPD51218A, IS61LPD25636A, IS61LPD51218A

TEST DATA OUT (TDO)

The TDO output pin is used to serially clock data-out fromthe registers. The output is active depending on the currentstate of the TAP state machine (see TAP Controller StateDiagram). The output changes on the falling edge of TCKand TDO is connected to the Least Significant Bit (LSB) ofany register.

ISSI

®

is set LOW (Vss) when the BYPASS instruction is ex-ecuted.

Boundary Scan Register

The boundary scan register is connected to all input andoutput pins on the SRAM. Several no connect (NC) pins arealso included in the scan register to reserve pins for higherdensity devices. The x36 configuration has a 75-bit-longregister and the x18 configuration also has a 75-bit-longregister. The boundary scan register is loaded with thecontents of the RAM Input and Output ring when the TAPcontroller is in the Capture-DR state and then placedbetween the TDI and TDO pins when the controller is movedto the Shift-DR state. The EXTEST, SAMPLE/PRELOADand SAMPLE-Z instructions can be used to capture thecontents of the Input and Output ring.

The Boundary Scan Order tables show the order in which thebits are connected. Each bit corresponds to one of thebumps on the SRAM package. The MSB of the register isconnected to TDI, and the LSB is connected to TDO.

PERFORMING A TAP RESET

A Reset is performed by forcing TMS HIGH (VDD) for fiverising edges of TCK. RESET may be performed while theSRAM is operating and does not affect its operation. Atpower-up, the TAP is internally reset to ensure that TDOcomes up in a high-Z state.

TAP REGISTERS

Registers are connected between the TDI and TDO pinsand allow data to be scanned into and out of the SRAM testcircuitry. Only one register can be selected at a timethrough the instruction registers. Data is serially loadedinto the TDI pin on the rising edge of TCK and output on theTDO pin on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into theinstruction register. This register is loaded when it isplaced between the TDI and TDO pins. (See TAP ControllerBlock Diagram)At power-up, the instruction register isloaded with the IDCODE instruction. It is also loaded withthe IDCODE instruction if the controller is placed in a resetstate as previously described.

When the TAP controller is in the CaptureIR state, the twoleast significant bits are loaded with a binary “01” patternto allow for fault isolation of the board level serial test path.

Scan Register Sizes

Register NameInstructionBypassID

Boundary Scan

Bit Size (x18)

313275

Bit Size (x36)

313275

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bitcode during the Capture-DR state when the IDCODEcommand is loaded to the instruction register. The IDCODEis hardwired into the SRAM and can be shifted out whenthe TAP controller is in the Shift-DR state. The ID registerhas vendor code and other information described in theIdentification Register Definitions table.

Bypass Register

To save time when serially shifting data through registers,it is sometimes advantageous to skip certain states. Thebypass register is a single-bit register that can be placedbetween TDI and TDO pins. This allows data to be shiftedthrough the SRAM with minimal delay. The bypass register

IDENTIFICATION REGISTER DEFINITIONS

Instruction FieldRevision Number(31:28)Device Depth(27:23)Device Width(22:18)ISSI Device ID(17:12)ISSI JEDEC ID(11:1)ID Register Presence(0)Description

Reserved for version number.Defines depth of SRAM. 256K or 512KDefines with of the SRAM. x36 or x18Reserved for future use.

Allows unique identification of SRAM vendor.Indicate the presence of an ID register.

256K x 36xxxx0011100100xxxxx00011010101

1

512K x 18xxxx0100000011xxxxx00011010101

1