Notes:

1.The specified values are valid when addresses are changed no more than once during tCK(min.) and when No

Operation commands are registered on every rising clock edge during tRC(min). Values are shown per modulebank.2.The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).

3.All AC characteristics are shown for device level.

An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.4.AC timing tests have VIL = 0.4V and VIH = 2.4V with the timing referenced to the 1.4V crossover point. The transition

time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuitshown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and witha input signal of 1V / ns edge rate between 0.8V and 2.0V.

CLOCK

50 Ohm

I/O

50 pF

INPUT

I/O

50 pF

1.4V

OUTPUT

Measurement conditions for

tac and toh

5.If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter.6.Rated at 1.5V

7.If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter.

8.Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be

given to “wake-up” the device.9.Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.

Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit commandis registered.10.

Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.

11.tDAL is equivalent to tDPL + tRP.

Package Diagram

L-DIM-168-30

SDRAM DIMM Module Package

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