MOSEL VITELIC

SPD-Table: (Continued)

V436632S04VTG-10PC

Hex Value

ByteNumber

30313233343536-61626364-125126127128+

Function Described

Minimum RAS Pulse Width tRASModule Bank Density (Per Bank)SDRAM Input Setup TimeSDRAM Input Hold TimeSDRAM Data Input Setup TimeSDRAM Data Input Hold Time

Superset Information (May be used in Future)SPD Revision

Checksum for Bytes 0 - 62

Manufacturers’s Information (Optional)Max. Frequency Specification100 MHz Support DetailsUnused Storage Location

SPD Entry Value

45 ns256 MByte2 ns1 ns2 ns1 ns

100 MHz-10PC

2D402010201000

Revision 1.2127C00

100 MHz64AF00

DC Characteristics

TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V

Limit Values

Symbol

VIHVILVOHVOLII(L)IO(L)

Parameter

Input High VoltageInput Low Voltage

Output High Voltage (IOUT = –4.0 mA)Output Low Voltage (IOUT = 4.0 mA)Input Leakage Current, any input

(0 V < VIN < 3.6 V, all other inputs = 0V)Output leakage current

(DQ is disabled, 0V < VOUT < VCC)

Min.

2.0–0.52.4—–40–40

Max.

VCC+0.30.8—0.44040

Unit

VVVVµAµA