GS8640V18/32/36T-300/250/200/167

AC Test Conditions

Parameter

Input high levelInput low levelInput slew rateInput reference levelOutput reference level

Output load

Conditions

VDD – 0.2 V0.2 V1 V/nsVDD/2VDDQ/2Fig. 1

1.Include scope and jig capacitance.

2.Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3.Device is deselected as defined by the Truth Table.

Output Load 1

DQ

50 VDDQ/2

* Distributed Test Jig Capacitance

30pF*

DC Electrical Characteristics

Parameter

Input Leakage Current(except mode pins)ZZ Input CurrentFT Input CurrentOutput Leakage CurrentOutput High VoltageOutput Low Voltage

Symbol

IILIIN1IIN2IOLVOH1VOL1

Test Conditions

VIN = 0 to VDDVDD ≥ VIN ≥ VIH0 V ≤ VIN ≤ VIHVDD ≥ VIN ≥ VIL0 V ≤ VIN ≤ VIL

Output Disable, VOUT = 0 to VDDIOH = –4 mA, VDDQ = 1.6 VIOL = 4 mA, VDD = 1.6 V

Min

–1 uA–1 uA–1 uA–100 uA–1 uA–1 uAVDDQ – 0.4 V

—

Max

1 uA1 uA100 uA1 uA1 uA1 uA—0.4 V