GS8640V18/32/36T-300/250/200/167

Simplified State Diagram with G

X

DeselectW

R

W

X

WCW

R

First Write

RCR

First Read

CR

CW

X

RCR

WBurst Write

Burst Read

CWCR

Notes:

1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3.Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.