GS8640V32T-250中文资料
发布时间:2021-06-05
发布时间:2021-06-05
元器件交易网
Product Preview
GS8640V18/32/36T-300/250/200/167
100-Pin TQFPCommercial TempIndustrial TempFeatures
operation
Single Cycle Deselect (SCD) operation 1.8 V +10%/–10% core power supply 1.8 V I/O supply
Internal input resistors on mode pins allow floating mode pins Default to Interleaved Pipeline mode
Internal self-timed write cycle
Automatic power-down for portable applications JEDEC-standard 100-lead TQFP package Pb-Free 100-lead TQFP package available
4M x 18, 2M x 32, 2M x 3672Mb Sync Burst SRAMs300 MHz–167 MHz
1.8 V VDD1.8 V I/O
Burst mode, subsequent burst addresses are generated counter may be configured to count in either linear or
Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by pin low places the RAM in Flow Through mode, causing high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable writing all bytes at one time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8640V18/32/36T operates on a 1.8 V power supply. All input are 1.8 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V compatible.
Functional Description
Applications
The GS8640V18/32/36T is a 75,497,472-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls
and power down control (ZZ) are asynchronous inputs. Burst
Parameter Synopsis
KQtCycle(x18)Curr (x32/x36)
KQtCycle(x18)Curr (x32/x36)
-3003.34805.5330
-2504.04106.5280
-2005.03507.5250
-1676.03058.0240
UnitnsmAnsmA
Pipeline3-1-1-1
Flow Through2-1-1-1
上一篇:20120615 深圳市香港卫视文化创意产业园项目建议
下一篇:数据库实验报告