Error Detection Block

You can enable the Stratix III device error detection block in the Quartus II software

(refer to“Software Support” on page15–11). This block contains the logic necessary to

calculate the 16-bit CRC signature for the configuration CRAM bits in the device.

The CRC circuit continues running even if an error occurs. When a soft error occurs,

the device sets the CRC_ERROR pin high. Two types of CRC detection check the

configuration bits:

■The CRAM error checking ability (16-bit CRC) during user mode, for use by the CRC_ERROR pin.

■For each frame of data, the pre-calculated 16-bit CRC enters the CRC circuit

right at the end of the frame data and determines whether or not there is an

error.

■If an error occurs, the search engine starts to find the location of the error.

■You can shift the error messages out through the JTAG instruction or core

interface logic while the error detection block continues running.

■The JTAG interface reads out the 16-bit CRC result for the first frame and also

shifts the 16-bit CRC bits to the 16-bit CRC storage registers for test purposes.

■You can deliberately introduce single error, double errors, or double errors

adjacent to each other to configuration memory for testing and design

verification.

1The “Error Detection Registers” section focuses on the first type, the 16-bit CRC only when the device is in user mode.

■The 16-bit CRC that is embedded in every configuration data frame.

■During configuration, after a frame of data is loaded into the Stratix III device,

the pre-computed CRC is shifted into the CRC circuitry.

■At the same time, the CRC value for the data frame shifted-in is calculated. If

the pre-computed CRC and calculated CRC values do not match, nSTATUS is

set low. Every data frame has a 16-bit CRC; therefore, there are many 16-bit

CRC values for the whole configuration bitstream. Every device has different

lengths of the configuration data frame.

Error Detection Registers

There is one set of 16-bit registers in the error detection circuitry that stores the

computed CRC signature. A non-zero value on the syndrome register causes the

CRC_ERROR pin to be set high. Figure15–1 shows the block diagram of the error

detection circuitry, syndrome registers, and error injection block.

Stratix III Device Handbook, Volume 1