AT45D081中文资料(6)

AT45D081

9

Read Operations

The following block diagram and waveforms illustrate the various read sequences available.

FLASH MEMORY ARRAY

PAGE (264 BYTES)

BUFFER 2 (264 BYTES)

BUFFER 1 (264 BYTES)

I/O INTERFACE

MAIN MEMORY

PAGE TO BUFFER 1

MAIN MEMORY PAGE TO BUFFER 2

MAIN MEMORY PAGE READ

BUFFER 1

READ

BUFFER 2READ

SO

Main Memory Page Read

SI CMD

PA6-0, BA8

BA7-0

X

X

X

X

CS n

n+1

SO

r r r, PA11-7

Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)

SI CMD

PA6-0, X

X

Starts reading page data into buffer

CS SO

r r r, PA11-7

Buffer Read

SI CMD

X

X···X, BFA8

BFA7-0

CS n

n+1

SO

X

Each transition represents 8 bits and 8 clock cycles

n = 1st byte read n+1 = 2nd byte read

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AT45D081

10

Detailed Bit-Level Read Timing – Inactive Clock Parity Low

Main Memory Page Read

Buffer Read

Status Register Read

SI

1

1

X

X

X

CS

SO

SCK

123456061626364656667

X

X

HIGH-IMPEDANCE

D 7D 6

D 5

DATA OUT

COMMAND OPCODE

MSB

tSU

tV

SI

1

1

X

X

X

CS

SO

SCK

123453637383940414243

X

X

HIGH-IMPEDANCE

D 7D 6

D 5

DATA OUT

COMMAND OPCODE

MSB

tSU

tV

SI

1

1

1

1

1

CS

SO

SCK

123457891011121617

HIGH-IMPEDANCE

D 7D 6

D 5

STATUS REGISTER OUTPUT

COMMAND OPCODE

MSB

tSU

tV

6D 1

D 0D 7LSB

MSB

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