FPGA实现双向IO口与时钟芯片的例子(3)
发布时间:2021-06-05
发布时间:2021-06-05
if( Done_Sig ) begin rLED <= Time_Read_Data[3:0]; isStart <= 8'd0; i <= 4'd4; end
else begin isStart <= 8'b0000_0010; end
endcase
wire Done_Sig;
wire [7:0]Time_Read_Data;
ds1302_module U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.Start_Sig( isStart ),
.Done_Sig( Done_Sig ),
.Time_Write_Data( rData ),
.Time_Read_Data( Time_Read_Data ),
.RST( RST ),
.SCLK( SCLK ),
.SIO( SIO )
);
assign LED = rLED;
Endmodule
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