assign Done_Sig = isDone;

assign Time_Read_Data = rRead;

assign Access_Start_Sig = isStart;

assign Words_Addr = rAddr;

assign Write_Data = rData;

Endmodule

module function_module

(

CLK, RSTn,

Start_Sig,

Words_Addr,

Write_Data,

Read_Data,

Done_Sig,

RST,

SCLK,

SIO

);

input CLK;

input RSTn;

input [1:0]Start_Sig;

input [7:0]Words_Addr;

input [7:0]Write_Data;

output [7:0]Read_Data;