FPGA实现双向IO口与时钟芯片的例子(14)

begin isOut <= 1'b0; i <= i + 1'b1; end

18, 20, 22, 24, 26, 28, 30, 32 : if( Count1 == T0P5US ) i <= i + 1'b1;

else begin rSCLK <= 1'b1; end

19, 21, 23, 25, 27, 29, 31, 33 : if( Count1 == T0P5US ) begin i <= i + 1'b1; end

else begin rSCLK <= 1'b0; rData[ (i >> 1) - 9 ] <= SIO; end

34 :

begin rRST <= 1'b0; isOut <= 1'b1; i <= i + 1'b1; end

35 :

begin isDone <= 1'b1; i <= i + 1'b1; end

36 :

begin isDone <= 1'b0; i <= 6'd0; end

endcase

assign Read_Data = rData;

assign Done_Sig = isDone;

assign RST = rRST;

assign SCLK = rSCLK;

assign SIO = isOut ? rSIO : 1'bz;