FPGA实现双向IO口与时钟芯片的例子(12)
发布时间:2021-06-05
发布时间:2021-06-05
begin
i <= 6'd0;
rData <= 8'd0;
rSCLK <= 1'b0;
rRST <= 1'b0;
rSIO <= 1'b0;
isOut <= 1'b0;
isDone <= 1'b0;
end
else if( Start_Sig[1] )
case( i )
0 :
begin rSCLK <= 1'b0; rData <= Words_Addr; rRST <= 1'b1; isOut <= 1'b1; i <= i + 1'b1; end
1, 3, 5, 7, 9, 11, 13, 15 : if( Count1 == T0P5US ) i <= i + 1'b1;
else begin rSIO <= rData[ (i >>
1) ]; rSCLK <= 1'b0; end
2, 4, 6, 8, 10, 12, 14, 16 : if( Count1 == T0P5US ) i <= i + 1'b1;
else begin rSCLK <= 1'b1; end
17 :
begin rData <= Write_Data; i <= i + 1'b1; end
18, 20, 22, 24, 26, 28, 30, 32 : if( Count1 == T0P5US ) i <= i + 1'b1;
else begin rSIO <= rData[ (i >>
1) - 9 ]; rSCLK <= 1'b0; end
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