ug_intro_to_megafunctions(8)

UG-01056-3.0

May2013

8ExampleTop-LevelVerilogModule

ExampleTop-LevelVerilogModule

VerilogHDLALTFP_MULTinTop-LevelModulewithOneInputConnectedtoMultiplexer.moduleMF_top(a,b,sel,datab,clock,result);

input[31:0]a,b,datab;inputclock,sel;

output[31:0]result;wire[31:0]wire_dataa;

assignwire_dataa=(sel)?a:b;

altfp_multinst1(.dataa(wire_dataa),.datab(datab),.clock(clock),.result(result));

defparam

inst1.pipeline=11,inst1.width_exp=8,inst1.width_man=23,

inst1.exception_handling="no";

endmodule

ExampleTop-LevelVHDLModule

VHDLALTFP_MULTinTop-LevelModulewithOneInputConnectedtoMultiplexer.libraryieee;

useieee.std_logic_1164.all;libraryaltera_mf;

usealtera_mf.altera_mf_components.all;

entityMF_topis

port(clock,sel:instd_logic;

a,b,datab:instd_logic_vector(31downto0);result:outstd_logic_vector(31downto0));

endentity;

architecturearch_MF_topofMF_topis

signalwire_dataa:std_logic_vector(31downto0);begin

wire_dataa<=awhen(sel='1')elseb;inst1:altfp_mult

genericmap(

pipeline=>11,width_exp=>8,width_man=>23,

exception_handling=>"no")

portmap(

dataa=>wire_dataa,datab=>datab,clock=>clock,result=>result);

endarch_MF_top;

AlteraCorporation

IntroductiontoMegafunctionIPCores