使用Verilog语言实现密勒码编译码器设计,课程实验。

//本进程用来并串转换

always @ (posedge clk2)

begin

if(c_finish==1) //解码完毕，可以输出鸟

begin

o_start=1;

signal_out<=outbuf_parallel[k];

k<=k-1;

if(k==0) //数据输出完毕

begin

o_finish=1;

signal_out<=0;

end

end

else

begin

signal_out<=0;

end

end

//本进程用来解码计算思密达

always @(posedge clk)

begin

if(d_finish==1) //串并转换完毕

begin

for(i = 16;i >= 3;i = i - 2)

case({datain_parallel[i],datain_parallel[i-1]})

2'b00:

outbuf_parallel[i/2]=2'b0;

2'b01:

outbuf_parallel[i/2]=2'b1;

2'b10:

outbuf_parallel[i/2]=2'b1;

2'b11:

outbuf_parallel[i/2]=2'b0;

endcase

case ({datain_parallel[2],datain_parallel[1]})

2'b00:

outbuf_parallel[i/2] = 2'b0;

2'b01:

outbuf_parallel[i/2] = 2'b1;

2'b10:

outbuf_parallel[i/2] = 2'b1;