MAX6319LHUK44B-T中文资料(9)

5-Pin µP Supervisory Circuits with Watchdog and Manual ResetMAX6316–MAX6322

Figure 7. Watchdog Timing Relationship

Figure 8. Ensuring RESETValid to VCC= 0 on Active-LowPush/Pull and Bidirectional Outputs

Watchdog Input Current

The WDI input is internally driven through a buffer andseries resistor from the watchdog counter. For minimumwatchdog input current (minimum overall power con-sumption), leave WDI low for the majority of the watch-dog timeout period. When high, WDI can draw as muchas 160µA. Pulsing WDI high at a low duty cycle willreduce the effect of the large input current. When WDIis left unconnected, the watchdog timer is servicedwithin the watchdog timeout period by a low-high-lowpulse from the counter chain.

Negative-Going VCCTransients

These supervisors are immune to short-duration, nega-tive-going VCCtransients (glitches), which usually donot require the entire system to shut down. Typically,200ns large-amplitude pulses (from ground to VCC) onthe supply will not cause a reset. Lower amplitude puls-es result in greater immunity. Typically, a VCCtransientthat goes 100mV under the reset threshold and lastsless than 4µs will not trigger a reset. An optional 0.1µFbypass capacitor mounted close to VCCprovides addi-tional transient immunity.

Figure 9. Ensuring RESET Valid to VCC= 0 on Active-HighPush/Pull Outputs

source current. This scheme does not work with theopen-drain outputs of the MAX6320/MAX6321/MAX6322.The resistor value used is not critical, but it must belarge enough not to load the reset output when VCCisabove the reset threshold. For most applications,100kΩis adequate.

Ensuring Valid Reset Outputs

Down to VCC= 0

The MAX6316_/MAX6317H/MAX6318_H/MAX6319_H/MAX6321HP/MAX6322HP are guaranteed to operateproperly down to VCC= 1V. In applications that requirevalid reset levels down to VCC= 0, a pulldown resistorto active-low outputs (push/pull and bidirectional only,Figure 8) and a pullup resistor to active-high outputs(push/pull only, Figure 9) will ensure that the reset line

is valid while the reset output can no longer sink or

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Watchdog Software Considerations

(MAX6316/MAX6317/MAX6318/

MAX6320/MAX6321)

One way to help the watchdog timer monitor softwareexecution more closely is to set and reset the watchdoginput at different points in the program, rather thanpulsing the watchdog input high-low-high or low-high-low. This technique avoids a stuck loop, in which thewatchdog timer would continue to be reset inside theloop, keeping the watchdog from timing out.

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5-Pin µP Supervisory Circuits with

Watchdog and Manual Reset

Figure 10 shows an example of a flow diagram wherethe I/O driving the watchdog input is set high at thebeginning of the program, set low at the end of everysubroutine or loop, then set high again when the pro-gram returns to the beginning. If the program shouldhang in any subroutine, the problem would be quicklycorrected, since the I/O is continually set low and thewatchdog timer is allowed to time out, causing a resetor interrupt to be issued. As described in the WatchdogInput Currentsection, this scheme results in higher timeaverage WDI current than does leaving WDI low for themajority of the timeout period and periodically pulsing itlow-high-low.

Figure 10. Watchdog Flow Diagram

__________________Pin Configurations

Typical Operating Circuit

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MAX6316–MAX6322